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ADV7195
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 22 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
This control bit delays the Y signal with respect to the falling
The CGMS data bits are programmed into the CGMS Data
Registers 0–2. For more information refer to CGMS Data
Registers section.
CGMS CRC (MR27)
This bit enables the automatic Cyclic Redundancy Check when
CGMS is enabled.
NO DELAY
edge of the horizontal sync signal by up to four pixel clock
cycles. Figure 21 demonstrates this facility.
Color Delay (MR23–MR25)
This control allows delay of the color signals with respect to the
falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 21 demonstrates this facility.
CGMS Enable (MR26)
When this bit is set to “1,” CGMS data is inserted on Line
41 in 525p mode. The CGMS conforms to CGMS-A EIA-J
CPR1204-1, Transfer Method of Video ID information using
vertical blanking interval (525p System), March 1998 and
IEC61880, 1998, video systems (525/60)—video and accompanied
data using the vertical blanking interval—analog interface.
Y DELAY
PrPb DELAY
Y OUTPUT
MAX DELAY
NO DELAY
PrPb OUTPUT
MAX
DELAY
Figure 21. Y and Color Delay
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
CGMS ENABLE
MR26
COLOR DELAY
MR25 MR24 MR23
Y DELAY
MR22 MR21 MR20
0 DISABLE
1 ENABLE
CGMS CRC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR27
0 DISABLE
1 ENABLE
Figure 22. Mode Register 2
REV. A
–17 –
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